The present invention relates generally to a semiconductor interconnect structure and particularly to a semiconductor interconnect structure for communicating a signal between an electrically conductive layer and a semiconductor layer of a sensor.
As feature sizes of integrated circuits continue to decrease it is desirable to minimize the number of processing steps required to fabricate an integrated circuit (IC) in order to increase the number of good integrated circuit die per semiconductor wafer (yield). It is clearly understood in the semiconductor processing art that each processing step has the potential to introduce micro contamination and processing defects that can result in a defective semiconductor and a subsequent reduction in yield per wafer. Additionally, defects introduced during the fabrication process may not surface until the IC becomes part of a finished product that later fails due to the defect in the IC.
Furthermore, it is desirable to simplify IC topography by making layers of the IC planar for the following reasons. First, reliability can be improved by eliminating IC features that have raised portions, abrupt edges, or sharp feature edges, such as conductive electrodes on which a semiconductor layer will be deposited, for example. Those features can introduce step coverage defects at the feature edges such as voids, pinholes, and the like.
Second, when possible, it is desirable to interface one layer of an IC to another layer using a planar surface to eliminate step coverage problems and to eliminate additional processing steps to planarize the layer for a subsequent process step such as a deposition step, for example. A planar surface can also increase adhesion between a contact and a semiconductor layer deposited on the contact. Adhesion can be enhanced by polishing a surface of the contact until the surface is smooth, for example.
Third, interconnect structures that interface different levels of an IC can introduce contact resistance due to various materials and interfaces in the interconnect structure. The contact resistance between a contact and a semiconductor layer can be reduced by eliminating unnecessary intervening structure. Ideally, the contact resistance is reduced to a minimum by making as direct a connection as possible between the contact and the semiconductor layer. Additional benefits from reducing the contact resistance include lower electromigration and reduced power consumption. As circuit feature sizes continue to decrease, lower contact resistance plays an important role in overall IC costs because the cost of packaging is directly related to the amount of waste heat that must be removed from the IC.
Fourth, by eliminating unnecessary topography in a interconnect structure the number of process steps is reduced thereby lowering manufacturing cost, increasing yield, and improving reliability. Fifth, polishing the surface of the contact can produce a mirror like finish that can be used to reflect light incident on the surface back into a semiconductor layer deposited over the contact. If the semiconductor layer is portion of an image sensor such as an amorphous silicon P-I-N photodiode, for example, the reflected light can increase the quantum efficiency of the image sensor.
Topography of prior art interconnect structures includes damascene contacts with two or more barrier layers, vertically stacked damascene contacts, and damascene contacts with integral etch stops.
The two barrier layer damascene contact consists of a first dielectric layer deposited on a semiconductor substrate. A trench is formed in the dielectric layer and a first barrier layer is conformally deposited on sidewall and bottom surfaces of the trench followed by a deposition of a conductive layer such as copper on top of the first barrier layer. The conductive layer is then etched until it is coplanar with a surface of the first dielectric layer. A second barrier layer is then deposited on the surface of the first dielectric layer. The second barrier layer completely covers the conductor. A second dielectric layer is then deposited on top of the second barrier layer. The second dielectric is patterned and then etched down through the second barrier layer to the conductive layer thereby exposing the planar surface of the conductive layer. When copper is used as the conductor the two barrier layers operate to prevent out-diffusion of the copper into the surrounding dielectric layer. The disadvantage of this structure is that the second barrier layer and the second dielectric layer require additional deposition, patterning, and etching steps. The resulting structure is not suitable for making a connection between a conductive layer and a semiconductor layer because the planar conductor surface is positioned at the bottom of a trench created by the second dielectric layer thereby requiring the semiconductor layer to fill the trench in order to make contact with the conductive layer.
Vertically stacked damascene contacts are similar to the foregoing except that a first damascene contact is formed in a first dielectric layer and a second dielectric layer is formed on top of the first dielectric layer, completely covering the first damascene contact. A second damascene contact is formed in the second dielectric layer in alignment with the first damascene contact. Each damascene contact has two barrier layers, and an additional barrier layer is positioned between the contacts. Vertically stacked damascene contacts are structurally more complex and therefore require even more processing steps than a single damascene contact with a resulting decrease in IC yield.
A damascene contact with an integral etch stop is formed by depositing a dielectric layer over a conductive layer and then patterning and etching a trench in the dielectric layer. The trench does not extend to the conductive layer. A conformal etch barrier material is deposited on an upper surface of the dielectric layer, sidewall surfaces of the trench, and a bottom surface of the trench. A pattern for a via opening is aligned with the sidewall surfaces of the trench and then patterned on the bottom surface of the trench. The via opening is then etched to form a via that extends from the bottom surface to the conductive layer. The etching does not remove the barrier material on the sidewall surfaces. The resulting via is narrower than the trench. The trench and the via are then completely filled with a conductive material, followed by polishing the conductive material to form a damascene contact. The disadvantage of using an etch stop is that the via opening must be perfectly aligned with the trench and etch selectivity of the etch barrier material must be selected to prevent etching of the sidewall barrier material during the via etch step. A potential defect can be introduced if the etch barrier is breached during the etch step. The extra steps of depositing, patterning, and etching the barrier material add to the process complexity and therefore have a direct impact on yield. Another disadvantage of using an etch barrier is that after the etch step the etch barrier serves no functional purpose in the damascene contact.
An additional disadvantage of the aforementioned trench structure for a damascene contact is the trench is not suitable for making a direct and discrete connection to a semiconductor layer such as a node of a discrete image sensor. In an image sensor having from several thousand to over a million image pixels it is desirable to make an efficient, direct, and discrete connection to an individual pixel in the image sensor using a discrete damascene contact.
From the foregoing it will be apparent that desirable attributes for a damascene contact to sensor include reducing the number of process steps required to fabricate the damascene contact, increased quantum efficiency, a planar topography, increased surface adhesion, reduced contact resistance, and direct and discrete connection to a semiconductor layer of a sensor.